Offset Pipelined Scheduling for Coarse Grain Reconfigurable Architectures
نویسندگان
چکیده
Coarse Grain Reconfigurable Arrays (CGRAs) offer improved energy efficiency and performance over conventional architectures. However, the limitations of modulo counter oriented execution on these devices restricts their broader application. This paper introduces the Offset Pipelining execution model and an associated scheduling algorithm to address these limits. The proposed approach broadens the scope of applications that can be efficiently mapped to CGRA architectures while mitigating the challenges of scalability and application development. A pipelined program counter CGRA framework blends the high parallelism of traditional CGRAs with the flexibility of commodity processors. Applications scheduled to take advantage of Offset Pipelining provide an average 1.94X speed up compared to a modulo scheduled implementation for resource limited scenarios. Resource utilization is 0.56X that of modulo scheduling to achieve performance parity. Offset Pipelining offers improved performance and flexibility for CGRAs.
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